Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device having a structure miniaturizable through simple fabrication steps and a method of fabricating a semiconductor device capable of remarkably improving production efficiency are obtained. The semiconductor device comprises a semiconductor chip including a semiconductor circuit having a prescribed function and an electrode on one main surface, a wire having a first end connected with the electrode and a second end having a connecting terminal connected to an external device and an insulator sealing at least the main surface of the semiconductor chip. The connecting terminal provided on the second end of the wire is a part formed while keeping a state integrated with the remaining part of the wire, and exposed on a bottom surface opposite to the upper surface of the insulator closer to the main surface.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod of fabricating the same, and more particularly, it relates to aminiaturized semiconductor device capable of remarkably improvingproduction efficiency and a method of fabricating the same.

[0003] 2. Description of the Prior Art

[0004]FIG. 95 is a sectional block diagram showing an exemplaryconventional semiconductor device. A semiconductor chip 101 a formed ona wafer is mounted on a die pad 105 b of a lead frame. Electrode pads103 of the semiconductor chip 101 a are connected with external leads105 a serving as external connecting terminals by wires 102. The wires102 form wire connecting terminals 102 b on portions con connected withthe electrode pads 103, while forming wire connecting terminals 102 a onportions connected with the external leads 105 a. Portions excludingexternal terminals of the external leads 105 a are sealed withinsulating resin 104, as shown in FIG. 95.

[0005] FIGS. 96 to 100 show a method of fabricating the aforementionedsemiconductor device. As shown in FIG. 96, a plurality of semiconductorcircuit areas (semiconductor chip regions) 101 a are arranged and formedon the wafer 101, for providing the electrode pads 103 on the surface ofeach semiconductor chip 101 a. As shown in FIG. 97, the wafer 101 is cutin units of the semiconductor chip regions 101 a, for obtaining eachfragmented semiconductor chip 101 a. Thereafter the fragmentedsemiconductor chip 101 a is fixed to the die pad 105 b of the leadframe, as shown in FIG. 98. Then, the electrode pads 103 arranged on theupper surface of the semiconductor chip 101 a and the external leads 105a are connected with each other by the wires 102, as shown in FIG. 99.Thereafter the portions excluding the terminals of the external leads105 a are sealed with the resin 104, as shown in FIG. 100. Finally,portions of the external leads 105 a exposed from the sealing resin 104are bent inward for reducing the size, thereby fabricating thesemiconductor device shown in FIG. 95.

[0006] A semiconductor device such as a DRAM (dynamic random accessmemory), for example, having excellent reliability can be obtained bythe aforementioned fabrication method.

[0007] However, the aforementioned semiconductor device employs the leadframe, and hence the external leads 105 a are inevitably located outsidethe semiconductor chip 101 a in a planar view. In order to eliminatesuch a factor inhibiting the semiconductor device from miniaturization,some proposals have heretofore been made. For example, FIG. 101 shows astructure proposed in Japanese Patent Laying-Open No. 9-162348 (1997).Referring to FIG. 101, resin projections 104 a covered with metal films115 a are provided on the bottom of a semiconductor chip 101 a forconnecting the metal films 115 a with electrode pads 103 of thesemiconductor chip 101 a with wires 102. According to this structure, noterminals for external connection are provided outside sealing resin,and hence this semiconductor device can be miniaturized.

[0008]FIG. 102 shows another structure proposed in Japanese PatentLaying-Open No. 10-98133 (1998). Referring to FIG. 102, externalconnection means 125 a is arranged in proximity to a semiconductor chip101 a without employing a lead frame. In this semiconductor device, thesemiconductor chip 101 a and the external connection means 125 a aresealed with resin 104 and exposed on the back surface. Thissemiconductor device can also be miniaturized due to the externalconnection means 125 a located inside the sealing resin 104 in a planarview.

[0009] However, the structure according to Japanese Patent Laying-OpenNo. 9-162348 shown in FIG. 101 requires pattern formation for the metalfilms 115 a covering the resin projections 104 a. Therefore, the numberof fabrication steps is complicatedly increased. Thus, the fabricationcost is increased, and the yield may be reduced.

[0010] In the structure according to Japanese Patent Laying-Open No.10-98133 shown in FIG. 102, an additional member, i.e., the externalconnection means 125 a must be arranged during fabrication steps.Therefore, the fabrication steps are complicated to increase thefabrication cost, and the yield may be reduced.

[0011] In addition, each of the aforementioned semiconductor devices isgenerally fabricated by cutting a wafer provided with semiconductorchips through prescribed processing steps along sections of the waferfor obtaining fragmented individual semiconductor chips. According to ageneral fabrication method, each of the semiconductor devices shown inFIGS. 96 to 100 is fabricated through a step of fragmenting thesemiconductor chip in advance of a step of sealing portions of the waferwith resin.

[0012] When electrode pads of the semiconductor chip and connectingterminals are wire-bonded and sealed with resin through the step offragmenting the semiconductor chip, alignment etc. must be performed ineach fragmented semiconductor chip, leading to limitation of theproduction efficiency. While the price of a semiconductor device isreduced by mass production for facilitating popularization of thesemiconductor device, the aforementioned system fabricating asemiconductor package for each fragmented semiconductor chip isproblematic in view of mass productivity.

[0013] In the aforementioned method fabricating the semiconductorpackage for each fragmented semiconductor device, it is difficult tohandle the semiconductor device when the same is miniaturized. It isobviously difficult to handle the aforementioned semiconductor deviceshown in FIG. 101 or 102 when the same is miniaturized.

[0014] Further, complicated processing steps are required forfabricating a semiconductor device such as the aforementionedminiaturized semiconductor device shown in FIG. 101 or 102 by stacking aplurality of individual fragmented semiconductor chips, and the finishedsemiconductor device is also complicated in structure. FIG. 103 shows amultilayer structure employing a lead frame. Referring to FIG. 103, thesizes of stacked semiconductor chips 101 a must be gradually reduced inascending order, and hence the number of stackable layers of thesemiconductor chips 101 a is limited. FIG. 104 shows a multilayerstructure formed by stacking semiconductor chips 101 a of the same size.It is understood from FIG. 104 that the semiconductor chips 101 a of thesame size must be stacked through a spacer 111. When the spacer 111 isemployed, not only the structure is complicated but also a connectingstep is required for each layer. Therefore, fabrication efficiency isdisadvantageously reduced.

SUMMARY OF THE INVENTION

[0015] An object of the present invention is to provide a miniaturizedsemiconductor device capable of remarkably improving productionefficiency and a method of fabricating this semiconductor device.

[0016] The semiconductor device according to the present inventioncomprises a semiconductor chip including a semiconductor circuit havinga prescribed function and an electrode on a main surface, a metal wirehaving a first end connected with the electrode and a second end havinga connecting terminal connected with an external device and an insulatorcovering at least the main surface of the semiconductor chip. In thissemiconductor device, the connecting terminal provided on the second endof the metal wire is a part formed while keeping a state integrated withthe remaining part of the metal wire, and exposed on a bottom surfaceopposite to the upper surface of the insulator.

[0017] According to the aforementioned structure, the connectingterminal integrally formed with the metal wire is exposed from thebottom. When the semiconductor device is fabricated, therefore, the partof the connecting terminal continuous with the metal wire connects theaforementioned electrode, a tentative conductive or support plate, forexample, and the connecting terminal integrally formed with the metalwire with each other. The aforementioned connecting terminal and theterminal part provided on the electrode are integrally formed with themetal wire. The connecting terminal and the terminal part provided onthe electrode may be formed in a step of arranging the metal wire whilekeeping the state integrated with the remaining part of the metal wire.At this time, the part for defining the connecting terminal may bedeformed by working. Therefore, (1) no seam is present between theconnecting terminal and the remaining part of the metal wire, and (2)the connecting terminal and the remaining part of the metal wire aresubstantially identical in composition to each other. The connectingterminal and the terminal part provided on the electrode may allowedlybe different in shape from the metal wire. When the metal wire isprepared from a wire, for example, the connecting terminal is broughtinto the form of a ball bond or a stitch bond by working the wire in awire connection step. When the metal wire is formed by gas deposition orplating, the connecting terminal can be brought into an arbitrary formsuitable for serving as a connecting part. The aforementioned tentativeconductive or support plate can be removed in a later step.

[0018] When forming the metal wire by a wire, for example, the followingworking can be performed in a wire bonding step:

[0019] (a) The forward end of the wire is connected to the electrode ofthe aforementioned semiconductor chip, for forming a first pressurecontact part. Then, a second pressure contact part is similarly formedalso on the aforementioned tentative conductive plate, so that the wirecontinuous to a supply source in a bonding tool can be cut. When thesecond pressure contact part is formed on the tentative conductiveplate, the wire is crushed to be increased in width. Therefore, the wirecan be employed as the connecting terminal. Wire bonding conditions canbe adjusted for increasing the width of the wire beyond those of thepressure contact parts formed under general pressure contact conditions.In ultrasonic wire bonding of an aluminum wire, further, similarpressure contact parts are formed on both of aluminum wire connectingportions of the electrode provided on the semiconductor chip and thesupport plate respectively. Also in this case, the pressure contactparts of the aluminum wire, merely connected onto the tentativeconductive plate, are increased in width. Therefore, the aluminum wirecan be readily employed as the connecting terminal. Further, thepressure contact parts can be worked in a larger width than those ofgeneral pressure contact parts by adjusting conditions for theultrasonic wire bonding.

[0020] (b) It is also possible to melt the forward end portion of thewire for forming a bulk part and forming a ball bond on the tentativeconductive plate and thereafter form a stitch bond on the electrode ofthe semiconductor chip.

[0021] (c) It is also possible to melt the forward end portion of thewire for forming a bulk part and forming a ball bond on the electrode ofthe semiconductor chip and thereafter form a stitch bond on thetentative conductive plate.

[0022] Through any of the steps (a), (b) and (c), the connectingterminal can be formed by the end of the metal wire worked and connectedto the conductive plate by removing the tentative conductive plate in alater step.

[0023] Consequently, a semiconductor device miniaturized by employing nolead frame can be fabricated through extremely simple fabrication steps.As a result, a miniaturized semiconductor device having high reliabilitycan be obtained at a low cost.

[0024] A method of fabricating semiconductor devices according to thepresent invention is a method of fabricating at least two semiconductordevices from a semiconductor substrate including at least twosemiconductor circuit areas provided with electrodes having prescribedfunctions for attaining electrical connection with an external devicearranged on a first main surface. This fabrication method comprisessteps of bonding a support plate to a second main surface of thesemiconductor substrate opposite to the first main surface, forming atrench for separating at least two semiconductor circuit areas intoindividual semiconductor circuit areas to expose the support platearound the semiconductor circuit areas, connecting the electrodes andthe support plate exposed in the trench with each other by a metal wire,and removing the support plate.

[0025] According to this method, semiconductor chips (the semiconductorcircuit areas) are not fragmented but connected to the support plate onthe bottom of the trench in the state supported by the support plate inthe step of connecting the electrodes and the support plate with eachother by the metal wire. When the aforementioned connecting step iscarried out through wire bonding, for example, the electrodes of thesemiconductor chips and connecting terminals are wire-bonded to eachother. Therefore, no alignment may be performed every conductor elementbut production efficiency can be remarkably improved. Thus, thefabrication method is remarkably excellent in view of mass productivity.

[0026] The fabrication method is also excellent in handleability cominginto question when performing miniaturization in a method of fabricatinga semiconductor package every fragmented semiconductor device.

[0027] Further, a semiconductor device having a multilayer structure canbe obtained by stacking semiconductor devices of the same size with norequirement for a complicated processing step. In addition, neither aspacer nor a specific circuit board may be employed at this time. Thus,the semiconductor device having a multilayer structure can be obtainedwithout limiting the number of the stacked layers.

[0028] A method of fabricating semiconductor devices according toanother aspect of the present invention is a method of fabricating atleast two semiconductor devices from a semiconductor substrate having atleast two semiconductor circuit areas provided with electrodes havingprescribed functions for attaining electrical connection with anexternal device arranged on a first main surface. This method offabricating semiconductor devices comprises steps of cutting thesemiconductor substrate into individual semiconductor circuit areas,bonding a support plate to a second main surface of the semiconductorsubstrate opposite to the first main surface, connecting the electrodeswith the support plate exposed in a trench by a metal wire, and removingthe support plate.

[0029] According to this method, electrodes of fragmented semiconductorchips and the support plate can be connected with each other by themetal wire. Therefore, the semiconductor devices can generally befabricated by employing a conventional fabrication line as such.

[0030] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 is a sectional block diagram showing a semiconductor deviceaccording to a first embodiment of the present invention;

[0032]FIG. 2 is a sectional block diagram showing a semiconductor deviceaccording to a second embodiment of the present invention;

[0033]FIG. 3 is a sectional block diagram showing a semiconductor deviceaccording to a third embodiment of the present invention;

[0034]FIG. 4 is a sectional block diagram showing a semiconductor deviceaccording to a fourth embodiment of the present invention;

[0035]FIG. 5 is a sectional view showing a stage after forming aplurality of circuit patterns for semiconductor chips on a wafer in amethod of fabricating semiconductor devices according to a fifthembodiment of the present invention;

[0036]FIG. 6 is a sectional view showing a stage after bonding a supportplate to the back surface of the wafer shown in FIG. 5;

[0037]FIG. 7 is a sectional view showing a stage after forming a trenchbetween circuit areas of the semiconductor chips shown in FIG. 6 bydicing;

[0038]FIG. 8 is a sectional view showing a stage after forming bulkconnecting terminals on support plate connecting parts for connectingthe support plate shown in FIG. 7 with electrodes of the semiconductorchips;

[0039]FIG. 9 illustrates a situation of forming a ball bond by wirebonding as each connecting terminal shown in FIG. 8;

[0040]FIG. 10 is a sectional view showing semiconductor devices in astage after forming resin patterns covering the semiconductor chips andthe wires shown in FIG. 8 with a space;

[0041]FIG. 11 is a sectional view showing the semiconductor devices in astage after removing the support plate shown in FIG. 10 by wet etching;

[0042]FIG. 12 is a sectional view of one of the semiconductor devicesfragmented from the state shown in FIG. 11;

[0043]FIG. 13 is a sectional view showing a stage after mounting thesemiconductor device of FIG. 12 on a circuit board;

[0044]FIG. 14 is a sectional view showing an example removing thesupport plate shown in FIG. 10 by polishing;

[0045]FIG. 15 is a sectional view showing another example removing thesupport plate shown in FIG. 10 by polishing;

[0046]FIG. 16 is a plan view, corresponding to FIG. 6, showing the stateof bonding the support plate to the back surface of the wafer afterforming the circuits of the semiconductor chips;

[0047]FIG. 17 is a plan view showing a stage after providing trenchesbetween the circuit areas of the wafer shown in FIG. 16 by dicing;

[0048]FIG. 18 is a plan view showing a stage after connecting electrodesof the semiconductor chips shown in FIG. 17 and the support plate witheach other by wires;

[0049]FIG. 19 is a sectional vie showing a stage after sealing thesemiconductor chips and the wires shown in FIG. 18 with resin atintervals by arranging the resin on intersections between the trenches;

[0050]FIG. 20 is a sectional view showing a stage after removing thesupport plate shown in FIG. 19;

[0051]FIG. 21 is a plan view of a semiconductor device, fragmented fromthe state shown in FIG. 20, as viewed from the back side;

[0052]FIG. 22 is a sectional view showing a stage after arranging asupport plate on the upper surfaces of semiconductor devices sealed withresin in a method of fabricating semiconductor devices according to asixth embodiment of the present invention;

[0053]FIG. 23 is a sectional view showing a stage after removing thesupport plate shown in FIG. 22;

[0054]FIG. 24 is a sectional view showing a stage after applying probesto exposed connecting terminals shown in FIG. 23 for testing theelectrical characteristics of the semiconductor devices;

[0055]FIG. 25 is a sectional view showing a stage after formingconnecting terminals, connecting the same by wires and thereafterforming upper connecting terminals on the connecting terminals in amethod of fabricating semiconductor devices according to a seventhembodiment of the present invention;

[0056]FIG. 26 is a sectional view showing a stage after forming resinpatterns by screen printing to cover semiconductor chips, the wires andthe connecting terminals shown in FIG. 25;

[0057]FIG. 27 is a sectional view showing a stage after removing asupport plate shown in FIG. 26;

[0058]FIG. 28 illustrates a semiconductor device fragmented by removingresin from an intersection between trenches shown in FIG. 27;

[0059]FIG. 29 is a sectional view showing a semiconductor device formedby successively stacking two semiconductor devices shown in FIG. 28;

[0060]FIG. 30 is a sectional view showing a stage after formingconnecting terminals, connecting the same by wires and thereafterforming upper connecting terminals on electrodes of semiconductor chipsin a method of fabricating semiconductor devices according to an eighthembodiment of the present invention;

[0061]FIG. 31 is a sectional view showing a stage after forming resinpatterns for exposing the upper connecting terminals from the uppersurfaces when covering the semiconductor chips, the wires and theconnecting terminals shown in FIG. 30 with resin;

[0062]FIG. 32 is a sectional view showing a stage after removing asupport plate shown in FIG. 31;

[0063]FIG. 33 illustrates a semiconductor device fragmented by removingresin from an intersection between trenches shown in FIG. 32;

[0064]FIG. 34 is a sectional view of a semiconductor device having atwo-layer structure formed by butt-jointing the bottom surfaces of thesemiconductor device show in FIG. 33 and a semiconductor deviceface-symmetrical thereto (the semiconductor device itself may correspondthereto) with each other;

[0065]FIG. 35 is a sectional view of a semiconductor device having atwo-layer structure formed by butt-jointing the upper surfaces of thesemiconductor device show in FIG. 33 and a semiconductor deviceface-symmetrical thereto (the semiconductor device itself may correspondthereto) with each other;

[0066]FIG. 36 is a sectional view showing a semiconductor device havinga four-layer structure formed by successively stacking two semiconductordevices having the two-layer structure shown in FIG. 35;

[0067]FIG. 37 is a sectional view of a semiconductor device having athree-layer structure according to the eighth embodiment of the presentinvention;

[0068]FIG. 38 is a sectional view showing a stage after forming sealingresin patterns to expose side portions of connecting terminals in amethod of fabricating semiconductor devices according to a ninthembodiment of the present invention;

[0069]FIG. 39 is a plan view of the semiconductor device shown in FIG.38;

[0070]FIG. 40 is a sectional view showing a stage after removing asupport plate sown in FIG. 38;

[0071]FIG. 41 is a plan view of a semiconductor device, fragmented byremoving resin from the intersection between the trenches shown in FIG.40, as viewed from the back side;

[0072]FIG. 42 is a sectional view showing a stage after mounting thesemiconductor device shown in FIG. 41 on a circuit board;

[0073]FIG. 43 is a sectional view showing a multilayer semiconductordevice formed by mounting the semiconductor devices shown in FIG. 41 onwall circuit boards;

[0074]FIG. 44 is a sectional view showing a semiconductor device of amultilayer structure formed by arranging the semiconductor devices shownin FIG. 41 on a wall circuit board while arranging no wall circuit boardon at least single sides but arranging planar circuit boards to projectoutward from the single sides;

[0075]FIG. 45 is a sectional view showing a semiconductor device of amultilayer structure formed by arranging the semiconductor device shownin FIG. 41 on a wall circuit board while arranging no wall circuit boardon at least single sides but arranging heat slingers to project outwardfrom the single sides;

[0076]FIG. 46 is a sectional view showing a stage after covering a waferwith resin to cover semiconductor chips and wires without employingresin pattern forming means in a method of fabricating semiconductordevices according to a tenth embodiment of the present invention;

[0077]FIG. 47 is a sectional view showing a stage after forming anisolation trench with a dicing saw to expose side portions of connectingterminals shown in FIG. 46;

[0078]FIG. 48 is a sectional view showing a semiconductor devicefragmented by removing a support plate shown in FIG. 47;

[0079]FIG. 49 illustrates two semiconductor devices according to aneleventh embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0080]FIG. 50 illustrates a state after polishing a wafer and formingelectrodes in fabrication of the semiconductor devices shown in FIG. 49;

[0081]FIG. 51 illustrates a state after bonding the support plate to theback surface of the wafer;

[0082]FIG. 52 illustrates a state after providing the trench reachingthe support plate through the wafer;

[0083]FIG. 53 illustrates a state after providing resist patterns;

[0084]FIG. 54 illustrates a state after forming metal wires by gasdeposition;

[0085]FIG. 55 illustrates a state after removing the resist patterns;

[0086]FIG. 56 illustrates a state sealed with sealing resin;

[0087]FIG. 57 illustrates a modification of the semiconductor deviceaccording to the eleventh embodiment of the present invention;

[0088]FIG. 58 illustrates another modification of the semiconductordevice according to the eleventh embodiment of the present invention;

[0089]FIG. 59 illustrates two semiconductor devices according to atwelfth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0090]FIG. 60 illustrates a state after mounding connecting terminalsupward on the support plate by gas deposition in fabrication of thesemiconductor devices shown in FIG. 59;

[0091]FIG. 61 illustrates a state after removing resist patterns;

[0092]FIG. 62 illustrates a state sealed with sealing resin;

[0093]FIG. 63 illustrates two semiconductor devices according to amodification of the twelfth embodiment of the present invention holdinga trench therebetween immediately after removal of a support plate;

[0094]FIG. 64 illustrates a gas deposition apparatus employed for amethod of fabricating semiconductor devices according to a thirteenthembodiment of the present invention;

[0095]FIG. 65 illustrates a method of forming a metal wire with theapparatus shown in FIG. 64;

[0096]FIG. 66 illustrates a method of forming a connecting terminal ofthe metal wires with the apparatus shown in FIG. 64;

[0097]FIG. 67 illustrates two semiconductor devices according to afourteenth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0098]FIG. 68 illustrates a state after forming insulator film patternsof polyimide or the like in fabrication of the semiconductor devicesshown in FIG. 67;

[0099]FIG. 69 illustrates a state after forming metal wires by gasdeposition;

[0100]FIG. 70 illustrates a state sealed with sealing resin;

[0101]FIG. 71 illustrates two semiconductor devices according to afifteenth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0102]FIG. 72 illustrates a state after forming patterns of sealingresin by screen printing, for example, in fabrication of thesemiconductor devices shown in FIG. 71;

[0103]FIG. 73 illustrates a state after forming metal wires by gasdeposition;

[0104]FIG. 74 illustrates a semiconductor device having a two-layerstructure according to a sixteenth embodiment of the present invention;

[0105]FIG. 75 illustrates two semiconductor devices according to aseventeenth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0106]FIG. 76 illustrates a state after forming a metal film by vapordeposition or the like in fabrication of the semiconductor devices shownin FIG. 75;

[0107]FIG. 77 illustrates a state after forming resist patterns;

[0108]FIG. 78 illustrates a state after forming metal wires byelectroplating;

[0109]FIG. 79 illustrates a state after removing the resist patterns;

[0110]FIG. 80 illustrates a state after removing the metal film byetching through masks of the metal wires;

[0111]FIG. 81 illustrates a state sealed with sealing resin;

[0112]FIG. 82 illustrates two semiconductor devices according to aneighteenth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate;

[0113]FIG. 83 illustrates a state after forming a second resist patternin fabrication of the semiconductor devices shown in FIG. 82;

[0114]FIG. 84 illustrates a state after forming on-electrode terminalson openings of the second resist pattern by second electroplating;

[0115]FIG. 85 illustrates a state after removing the resist pattern;

[0116]FIG. 86 illustrates a state sealed with sealing resin;

[0117]FIG. 87 illustrates a modification of the semiconductor devicesaccording to the eighteenth embodiment of the present invention;

[0118]FIG. 88 illustrates a semiconductor device according to anineteenth embodiment of the present invention;

[0119]FIG. 89 illustrates a first modification of the semiconductordevice according to the nineteenth embodiment of the present invention;

[0120]FIG. 90 illustrates a second modification of the semiconductordevice according to the nineteenth embodiment of the present invention;

[0121]FIG. 91 illustrates a third modification of the semiconductordevice according to the nineteenth embodiment of the present invention;

[0122]FIG. 92 illustrates a fourth modification of the semiconductordevice according to the nineteenth embodiment of the present invention;

[0123]FIG. 93 illustrates a fourth modification of the semiconductordevice according to the nineteenth embodiment of the present invention;

[0124]FIG. 94 illustrates a method of fabricating semiconductor devicesaccording to a twentieth embodiment of the present invention;

[0125]FIG. 95 is a sectional view showing a conventional semiconductordevice employing a lead frame;

[0126]FIG. 96 is a sectional view showing a stage after forming circuitareas of a plurality of semiconductor chips on a wafer in fabrication ofthe conventional semiconductor device shown in FIG. 95;

[0127]FIG. 97 is a sectional view showing a stage after separating thewafer shown in FIG. 96 into the respective semiconductor chips;

[0128]FIG. 98 is a sectional view showing a stage after loading one ofthe fragmented semiconductor chips shown in FIG. 97 on a lead frame;

[0129]FIG. 99 is a sectional view showing a stage after couplingelectrodes of the semiconductor chip shown in FIG. 98 with external leadparts;

[0130]FIG. 100 is a sectional view showing a stage after sealing asemiconductor device shown in FIG. 99 with resin;

[0131]FIG. 101 illustrates a conventional miniaturized semiconductordevice;

[0132]FIG. 102 illustrates another conventional miniaturizedsemiconductor device;

[0133]FIG. 103 illustrates a multilayer structure of a conventionalsemiconductor device; and

[0134]FIG. 104 illustrates another multilayer structure of aconventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0135] Embodiments of the present invention are now described withreference to the drawings.

[0136] First Embodiment

[0137] Referring to FIG. 1, a semiconductor chip 1 a and a wire 2 aresealed with insulating resin 4 in a semiconductor device according to afirst embodiment of the present invention. A first end 2 b of the wire 2is connected to an electrode 3 of the semiconductor chip 1 a, to formthe so-called stitch bond. A second end of the wire 2 defines a workedand bulked connecting terminal 2 a exposed from the sealing resin 4. Theexposed surface of the connecting terminal 2 a projects outward beyondthe semiconductor chip 1 a.

[0138] According to this structure, the connecting terminal 2 a can beformed by simply melting the second end of the wire 2. Thus, (a) thesemiconductor device can be readily miniaturized, and (b) the productionefficiency is remarkably improved and the fabrication cost can bereduced due to the extremely simplified structure. Further, theconnecting terminal 2 a projecting outward beyond the semiconductor chip1 a can be readily and reliably connected with another terminal withoutmuch improving the dimensional accuracy of this semiconductor device.

[0139] Second Embodiment

[0140] Referring to FIG. 2, the feature of a semiconductor deviceaccording to a second embodiment of the present invention resides inthat a plate member 6 is arranged on the back surface of a semiconductorchip 1 a. A metal plate can be generally employed for this plate member6. The plate member 6 can be readily formed by partially changing amethod of fabricating a semiconductor device described later.

[0141] The mechanical strength such as rigidity of the semiconductordevice can be improved by arranging the aforementioned plate member 6.When the plate member 6 is made of a heat conductive member such as ametal plate, heat radiation from the semiconductor chip 1 a can beimproved.

[0142] Third Embodiment

[0143] Referring to FIG. 3, the feature of a semiconductor deviceaccording to a third embodiment of the present invention resides in thata solder coat 7 is formed on a surface of a connecting terminal 2 aexposed on the back surface of the semiconductor device. The connectingterminal 2 a can be readily and reliably connected to a terminal of acircuit board or the like due to the formation of the solder coat 7, forattaining high connection strength.

[0144] Fourth Embodiment

[0145] Referring to FIG. 4, the feature of a semiconductor deviceaccording to a fourth embodiment of the present invention resides inthat a plate member is formed by a metal plate 6 arranged on the backsurface of a semiconductor chip, and this metal plate 6 is also coveredwith a solder coat 8 in addition to a connecting terminal 2 a. When thesemiconductor device is loaded on a circuit board, adhesion strength andheat radiation can be improved due to the formation of the solder coat8.

[0146] Fifth Embodiment

[0147] FIGS. 5 to 20 illustrate a method of fabricating semiconductordevices according to a fifth embodiment of the present invention. Any ofthe semiconductor devices according to the aforementioned first tofourth embodiments can be fabricated by this method. First, patternsprovided with circuit areas are formed on regions of respectivesemiconductor chips 1 a on the main surface of a wafer (semiconductorsubstrate) 1, as shown in FIG. 5. The circuit areas have prescribedfunctions, and include electrodes 3 for attaining electrical connectionwith an external device. The back surface of the wafer 1 may be groundand adjusted to a prescribed thickness, or may not be ground.

[0148] Then, a support plate 5 is bonded to the back surface of thewafer 1, as shown in FIG. 6. A metal plate of aluminum or the like canbe employed for the support plate 5. The support plate 5 is preferablybonded by anode connection. Alternatively, the support plate 5 can bebonded with an adhesive. Thereafter a trench 11 is so formed that aperipheral part of the circuit area of each semiconductor chip 1 areaches the support plate 5. This trench 11 can be formed with a dicingsaw, for example. The trench 11 passes through the wafer 1 to reach thesupport plate 5 and form a shallow groove also in the support plate 5.

[0149] Etching, plating or combination of etching and plating may becarried out on the exposed surface of the support plate 5, in order tofacilitate connection of wires 2 in a subsequent wire bonding step. Suchetching, plating or combination of etching and plating can be readilyperformed on the exposed part of the support plate 5 by generalprocessing. This processing is also effective for improving the strengthof the connected portions, in addition to the effect of implementingsimple and reliable connection of the wires 2.

[0150] Then, an electrode 3 of each semiconductor chip 1 a is connectedwith the support plate 5 located on the bottom portion of the trench 11by the so-called wire bonding (FIG. 8). A part of the wire 2 in contactwith the bottom of the trench 11 is melted into a spherical form, forforming the so-called ball bond. In wire bonding, the forward end of thewire 2 is discharged and melted in a wire bonding apparatus, for forminga bulk part (ball) 2 a. Then, the ball 2 a is properly grown andconnected to the support plate 5, as shown in FIG. 9. Then, the wire 2is supplied from a torch 15 and connected to the electrode 3 of thesemiconductor chip 1 a for forming a stitch bond. Alternatively, wirebonding conditions can be adjusted for forming the stitch bond on theelectrode 3 first and thereafter forming the ball bond on the supportplate 5.

[0151] Further, a dent or a through hole can be previously arranged onthe support plate 5 for pressing an end of the wire 2 with a torch andfitting/connecting the end in/to the dent or the through hole whenconnecting the end of the wire. Alternatively, the end of the wire canbe strongly pressed with a torch to be fitted/connected with the supportplate, without previously providing a dent or a through hole in thesupport plate. When the aforementioned connecting method is employed andetching is employed for removing the support plate in the later step,the end of the wire further projects outward. Consequently, theaforementioned connecting terminal can be further readily connected withanother terminal.

[0152] Then, the semiconductor chips 1 a and the wires 2 are coveredwith resin, which is an insulator, as shown in FIG. 10. At this time, athermosetting polymeric material having flowability is screen-printed sothat no resin is arranged in a space S between adjacent semiconductorchips 1 a. Depending on the situation, however, resin is arranged onintersections between trenches or the like so that semiconductor devicesare not fragmented immediately after the support plate 5 is removed.Alternatively, resin may be arranged in the space S in response to thesituation. Thereafter post-heat treatment is performed for hardening thethermosetting polymeric material.

[0153] Then, the support plate 5 is removed from the back surfaces ofthe semiconductor devices by wet etching, as shown in FIG. 11. Thesupport plate 5 can be removed by mechanical polishing or chemicalmechanical polishing (CMP), in place of wet etching. When mechanicalpolishing or CMP is employed, however, exposed surfaces of theconnecting terminals 2 a and the back surfaces of the semiconductorchips 1 a are flush with each other and no connecting terminals 2 a canproject outward beyond the semiconductor chips 1 a.

[0154] Then, the resin arranged on the intersections of the trenchesetc. is removed for forming fragmented semiconductor devices. When noresin is arranged in the space S including the intersections of thetrenches, however, the semiconductor devices are fragmented by removingthe support plate 5 and hence the resin arranged on the intersections ofthe trenches may not be removed.

[0155] Then, a solder coat 7 is formed on the connecting terminal 2 aexposed on the back surface of each semiconductor device, as shown inFIG. 12. The solder coat 7 can be employed as a jointing material. Amethod of forming this solder coat 7 may not be limited to plating butanother covering method can be employed. Then, the solder coat 7 isconnected with an electrode 13 provided on a circuit board 12 (FIG. 13).

[0156] Each of FIGS. 14 and 15 is a sectional view showing a state afterremoving the support plate 5 not by wet etching but by mechanicalpolishing or CMP. In this case, the exposed surfaces of the connectingterminals 2 a are flush with the back surfaces of the semiconductorchips 1 a as shown in FIG. 14, or parts 5 a of the support plate 5 maybe left on the back surfaces of the semiconductor chips 1 a as shown inFIG. 15 to be employed as the plate member 6 shown in FIG. 2.

[0157]FIG. 16 is a plan view showing a stage corresponding to thesectional view shown in FIG. 6. Circuit areas (semiconductor chips) 1 aprovided with circuits including electrodes 3 and having prescribedfunctions are formed on the wafer 1. The support plate 5 is bonded tothe back surface of the wafer 1 by anodic oxidation. Thereafter trenches11 are vertically and transversely formed to pass through the wafer 1from the upper surface thereof, while defining an intersection 1 a ofthe trenches 11 etc. The trenches 11 can be formed with a dicing saw.

[0158] Then, the electrodes 3 and the support plate 5 are connected witheach other by the wires 2, as shown in FIG. 18. At this time, the wirebonding conditions are adjusted to form the bulk connecting terminals 2a on the portions connected with the support plate 5. Then, portionsexcluding spaces S between the connecting terminals 2 a of adjacentsemiconductor devices are covered with resin 4,a s shown in FIG. 19.Resin 4 a is also arranged on positions corresponding to theintersections 11 a of the trenches 11.

[0159] Then, the support plate 5 is removed, thereby obtainingsemiconductor devices sealed with the resin 4 as shown in FIG. 20. Thesemiconductor devices are connected with each other by the resin 4 aarranged on the intersections 11 a of the trenches 11. FIG. 21 is a planview showing each semiconductor device fragmented by removing the resin4 a as viewed from the back surface. The connecting terminals 2 a formedfrom the wires 2 are arranged along edges of the semiconductor chip 1 a.

[0160] According to the aforementioned fabrication method, aminiaturized semiconductor device having a simple structure can beobtained through extremely simplified fabrication steps. Therefore, asemiconductor device improved in degree of integration can be fabricatedat a low cost.

[0161] Sixth Embodiment

[0162] FIGS. 22 to 24 illustrate a method of fabricating semiconductordevices according to a sixth embodiment of the present invention. Thefeature of this embodiment resides in the structure of the semiconductordevice subjected to determination of effectiveness/defectiveness. Aftera support plate 5 and electrodes 3 of semiconductor chips 1 a areconnected with each other by wires 2 and sealed with resin 4 (see FIG.10), an inspection support plate 25 is arranged on surfaces opposite tothe support plate 5, as shown in FIG. 22. The second support plate 25may be a film.

[0163] Then, the support plate 5 is removed by wet etching, as shown inFIG. 23. This wet etching may be replaced with mechanical polishing orCMP. Then, probes 16 are applied to exposed connecting terminals 2 a fordetermining effectiveness/defectiveness of circuit functions ofsemiconductor devices, as shown in FIG. 24.

[0164] According to the aforementioned method, the respectivesemiconductor chips 1 a can keep positions on a wafer also after thesupport plate 5 is removed. Therefore, the semiconductor chips 1 a maynot be individually transported for inspection but can be inspected inthe state arranged on the wafer, similarly to the prior art. Thus, it ispossible to efficiently inspect miniaturized semiconductor devicesfabricated through extremely simplified fabrication steps with probes ina state integrally arranged similarly to the prior art.

[0165] Seventh Embodiment

[0166] FIGS. 25 to 28 illustrate a method of fabricating semiconductordevices according to a seventh embodiment of the present invention.First, electrodes 3 of semiconductor chips 1 a and a support plate 5 areconnected with each other by wires 2 followed by formation of connectingterminals 2 a on the support plate 5 (FIG. 8), and thereafter upperterminals 22 are formed in contact with the upper portions of theconnecting terminals 2 a, as shown in FIG. 25. The upper terminals 22can be readily formed by wire bonding. Then, resin 4 is arranged onportions excluding a space S, for sealing the semiconductor chips 1 aand the wires 2. Resin is arranged also on intersections of trenches,for connecting respective semiconductor devices with each other. Theupper portions of the upper terminals 22 are exposed from the sealingresin 4.

[0167] Then, the support plate 5 is removed for obtaining semiconductordevices sealed with the resin 4, as shown in FIG. 27. Thereafter cornerportions provided with the resin 4 are cut for obtaining each fragmentedsemiconductor device, as shown in FIG. 28.

[0168] This semiconductor device is a semiconductor device 52 providedwith terminals on the same upper and lower positions. A miniaturizedsuccessively stacked semiconductor device, capable of high-densitypackaging, having a multilayer structure shown in FIG. 29 can beobtained by successively stacking such semiconductor devices 52 providedwith terminals on the same upper and lower positions. When such asemiconductor device of the multilayer structure is employed, thedensity of integration can be remarkably improved as compared with theprior art.

[0169] Eighth Embodiment

[0170] FIGS. 30 to 32 illustrate a method of fabricating semiconductordevices according to an eighth embodiment of the present invention.First, electrodes 3 of semiconductor chips 1 a and a support plate 5 areconnected with each other by wires 2 followed by formation of connectingterminals 2 a on the support plate 5 (FIG. 8), and thereafteron-electrode terminals 23 are formed in contact with the upper portionsof the electrodes 3, as shown in FIG. 30. The on-electrode terminals 23can also be readily formed by wire bonding.

[0171] Then, resin 4 is arranged on portions including corner portionsfor sealing the semiconductor chips 1 a and the wires 2 with the resin,as shown in FIG. 31. At this time, the upper surfaces of theaforementioned on-electrode terminals 23 are exposed from the resin 4.Then, the support plate 5 is removed for obtaining semiconductor devicessealed with the resin 4, as shown in FIG. 32. A fragmented semiconductordevice can be obtained by removing the resin 4 from intersections oftrenches (FIG. 33). This semiconductor device is provided on upper andlower portions with the connecting terminals 2 a and 23, which aredifferent in planar position from each other. Such a semiconductordevice is referred to as a semiconductor device 53 provided withterminals on different upper and lower positions. This semiconductordevice 53 has face-symmetrical arrangement as to a plane parallel to themain surface of the semiconductor chip 1 a.

[0172]FIG. 34 is a sectional block diagram showing a semiconductordevice having a two-layer structure assembled by butting the bottomsurfaces of two semiconductor devices 53 provided with terminals ondifferent upper and lower positions against each other. In the case offace-symmetrical arrangement, it follows that the connecting terminals 2a are connected with each other when the bottom surfaces thesemiconductor devices 53 are butted against each other. When thesemiconductor device 53 provided with terminals on different upper andlower positions shown in FIG. 33 has no face symmetry, the semiconductordevice having the two-layer structure shown in FIG. 34 cannot beobtained by employing two such semiconductor devices 53 provided withterminals on different upper and lower positions. When the semiconductordevice 53 has no face symmetry, another semiconductor device having facesymmetry with respect to the semiconductor device 53 shown in FIG. 33must be prepared for butting the same against the semiconductor device53 shown in FIG. 33 thereby attaining a two-layer structure. In thesemiconductor device having a two-layer structure shown in FIG. 34,therefore, the semiconductor device 53 shown in FIG. 33 preferably hasface symmetry.

[0173]FIG. 35 is a sectional block diagram showing a semiconductordevice having a two-layer structure assembled by butting the uppersurfaces of two semiconductor devices 53 provided with terminals ondifferent upper and lower positions against each other. In the case ofthe aforementioned face symmetry, it follows that upper connectingterminals 23 are connected with each other when the upper surfaces ofthe semiconductor devices 53 are butted against each other. Also in thetwo-layer structure shown in FIG. 35, the semiconductor device 53provided with terminals on different upper and lower positions shown inFIG. 33 must have face symmetry.

[0174] The semiconductor device of the two-layer structure shown in eachof FIGS. 34 and 35, external connecting terminals are flush with eachother in a planar view as a single integrated semiconductor device.Therefore, it is possible to fabricate a semiconductor device having aneven layer structure of at least four layers by successively stackingsuch semiconductor devices having a two-layer structure. For example,FIG. 36 is a sectional block diagram showing a semiconductor devicehaving a four-layer structure assembled by successively stacking twosemiconductor devices having a two-layer structure shown in FIG. 35.

[0175]FIG. 37 is a sectional block diagram showing a semiconductordevice having a three-layer structure as an exemplary semiconductordevice having an odd layer structure. The semiconductor device shown inFIG. 37 can be viewed as a semiconductor device formed by (a) connectingthe semiconductor device having a one-layer structure shown in FIG. 33to the lower connecting terminal 23 of the semiconductor device having atwo-layer structure shown in FIG. 34, or (b) connecting thesemiconductor device having a one-layer structure shown in FIG. 33 tothe upper connecting terminal 2 a of the semiconductor device having atwo-layer structure shown in FIG. 35.

[0176] When the connecting terminal 2 a exposed on the upper surface isprovided on the electrode 3 of the semiconductor chip 1 a as describedabove, (A) an inverted multilayer semiconductor device having amultilayer structure can be obtained by connecting an invertedsemiconductor device and the semiconductor device with each other if thesemiconductor device has the aforementioned face symmetry. (B) If thesemiconductor device has no face symmetry, an inverted multilayersemiconductor device having a multilayer structure can be obtained bypreparing a face-symmetrical semiconductor device and connecting theface-symmetrical counter semiconductor device and the semiconductordevice with each other in inverted arrangement.

[0177] The aforementioned semiconductor device, having an extremelysimplified miniature structure, can be readily fabricated at a low cost.

[0178] Ninth Embodiment

[0179]FIGS. 38 and 39 illustrate a method of fabricating semiconductordevices according to a ninth embodiment of the present invention.According to this embodiment, resin 4 is molded in resin sealing so thatside portions of connecting terminals 2 a are exposed from the sealingresin 4 at the time of or after resin sealing (FIG. 38). In other words,resin patterns may be so set as to expose the side portions of theconnecting terminals 2 a, or set as shown in FIG. 10 illustrating thefifth embodiment so that the side portions of the connecting terminals 2a are partially polished with a dicing saw and exposed after resinsealing. Further alternatively, the overall surface of a wafer may becovered with resin 4 without employing resin patterns, for exposing theside portions of the connecting terminals 2 a when cutting the wafer toseparate the connecting terminals 2 a of adjacent semiconductor devicesfrom each other.

[0180]FIG. 39 is a plan view in the stage shown in FIG. 38. It isunderstood that the side portions of the connecting terminals 2 a areexposed in this embodiment while the connecting terminals are coveredwith the resin 4 in the fifth embodiment as shown in FIG. 19. Accordingto this structure, the bottom surfaces and the side portions of theconnecting terminals 2 a are exposed from the sealing resin 4 after asupport plate 5 is removed, as shown in FIG. 40. FIG. 41 is a plan viewshowing a semiconductor device fragmented by segmenting corner potionscovered with the resin 4 or the like as viewed from the back surface. Ascompared with the plan view shown in FIG. 21, it is understood that theside potions of the connecting terminals 2 a are exposed.

[0181]FIG. 42 is a sectional view of the fragmented semiconductor devicemounted on a circuit board 12. The connecting terminal 2 a of thesemiconductor device is connected to a connecting terminal 13 of thecircuit board 12 through solder 7.

[0182]FIG. 43 is a sectional view showing a stage after fragmenting thesemiconductor devices shown in FIG. 40 and mounting the fragmentedsemiconductor devices on wall circuit boards 32. The wall circuit boards32 are provided with wired terminals 33, to which the side portions ofthe connecting terminals 2 a are connected through solder 37. The wallcircuit boards 32 can be arranged on four sides to enclose theperipheries of the semiconductor devices. The wall circuit boards 32 maynot be arranged on some sides at need.

[0183] In each of the aforementioned semiconductor devices having amultilayer structure, the side portion of a single connecting terminal 2a is utilized for connection with each wall circuit board 32 withoutnewly arranging a connecting terminal exposed on the upper portion ofthe semiconductor device. According to this embodiment, therefore, it ispossible to obtain a miniaturized semiconductor device having a simplestructure by an extremely simple fabrication method.

[0184]FIG. 44 is a sectional block diagram showing another semiconductordevice according to the ninth embodiment of the present invention. Whenhaving at least one side provided with no wall circuit board, thissemiconductor device having a multilayer structure comprises circuitboards 34 arranged to project outward from the side. In general, noconnecting terminals are arranged on the aforementioned side. In thesemiconductor device having a multilayer structure, wired connectingterminals 35 of the circuit boards 34 and the bottom surfaces ofconnecting terminals 2 a are connected with each other through solder37. The side portions of the connecting terminals 2 a are employed forconnecting terminals 33 to a terminal 33 of a wall circuit board 32.

[0185] According to this structure, it is possible to obtain aminiaturized multilayer semiconductor device having a simplifiedstructure without further providing terminals for external connection.This structure is superior in heat radiation to the structure shown inFIG. 43, and can ensure highly reliable operations followinghigh-density packaging. In combination with the structure of thesemiconductor device shown in FIG. 43, various connection with anexternal circuit can be attained.

[0186]FIG. 45 is a sectional block diagram showing still anothersemiconductor device according to the ninth embodiment of the presentinvention. In this semiconductor device, heat slingers 39 are connectedto plate members 6 provided on the back surfaces of semiconductor chips1 a without arranging circuit boards planarly placed in thesemiconductor device shown in FIG. 44. In general, heat conductors arepreferably arranged on the back surfaces of the semiconductor chips 1 ain view of relaxation of working accuracy or the like, such heatconductors are not necessarily required but the back surfaces of thesemiconductor chips 1 a may be in contact with the heat slingers 39.

[0187] A high heat radiation effect can be attained according to thisstructure, whereby highly reliable operations can be ensured whileensuring extremely high packaging density.

[0188] Tenth Embodiment

[0189] According to a tenth embodiment of the present invention, theoverall surface is covered with resin 4 as shown in FIG. 46 in resinsealing similar to that in the fifth embodiment (FIG. 10) withoutemploying pattern formation means such as screen printing. In otherwords, electrodes 3 of semiconductor chips 1 a and a support plate 5 areconnected with each other by wires 2, and thereafter the semiconductorchips 1 a and the wires 2 are filled up with the resin 4 along with aspace between semiconductor devices. Thereafter an isolation trenchhaving a width for exposing the side portions of connecting terminals 2a is formed with a dicing saw as shown in FIG. 47 before the supportplate 5 is removed. At this time, the connecting terminals 2 a may bepartially cut. This isolation trench, formed on the boundary between thesemiconductor devices for isolating the same from each other, has adepth reaching the support plate 5. Such isolation trenches arevertically and transversely formed to intersect with each other.Thereafter the support plate 5 is removed for fragmenting eachsemiconductor device as shown in FIG. 48. Thereafter a semiconductordevice having a multilayer structure can be formed by employing wallcircuit boards. Thus, a miniaturized semiconductor device having asimple structure can be obtained.

[0190] When the width of the trenches formed with the dicing saw isreduced in the aforementioned fabrication method, any of thesemiconductor devices according to the first to fourth embodiments canbe obtained.

[0191] When the aforementioned fabrication is employed, theaforementioned semiconductor device can be fabricated by a variousfabrication method at a low cost without employing pattern formationmethod such as screen printing for resin sealing. When a conductiveplate such as a metal plate is employed for the support plate 5, allelectrodes are shorted in the stages shown in FIGS. 46 and 47.Therefore, it is possible to prevent electrostatic discharge damagepossibly caused by cutting when forming trenches having a width forexposing the side portions of the electrodes.

[0192] Eleventh Embodiment

[0193]FIG. 49 illustrates semiconductor devices according to an eleventhembodiment of the present invention. Referring to FIG. 49 showing astate immediately after removing a support plate 5, the twosemiconductor devices are opposed to each other. While the wire isformed by wire bonding in each of the first to tenth embodiments, thefeature of this embodiment resides in that metal wires 18 formed by gasdeposition connect electrodes 3 of semiconductor chips 1 a and externalconnecting portions 18 a with each other.

[0194] A fabrication method in the case of performing the aforementionedconnection by gas deposition is now described. First, a wafer 1 ispolished to a prescribed thickness, followed by formation of theelectrodes 3 on prescribed portions of the surface of the wafer 1, asshown in FIG. 50. Thereafter the support pate 5 is bonded to the backsurface of the semiconductor wafer 1 (FIG. 51). The support plate 5 canbe formed by an aluminum plate. A trench 11 reaching the support plate 5is provided in the wafer 1 by dicing, to separate the semiconductorwafer 1 into the semiconductor chips 1 a (FIG. 52). Then, resistpatterns 17 are formed to expose prescribed portions of the electrodes 3and the trench 11 while covering the upper and side surfaces of thesemiconductor chips 1 a and the center of the trench 11 (FIG. 53).

[0195] Generally, the method may comprise a step of covering the firstmain surface of the semiconductor substrate with an insulator film(resist pattern) before the step of connecting the electrodes and thesupport plate with each other by the metal wire, and can form a metalfilm coming into contact with upper portions of the insulator film(resist pattern), the electrodes and the support plate by either gasdeposition or plating in the step of connecting the electrodes and thesupport plate with each other by the metal wire.

[0196] This insulator film is formed not to cover the electrodes of thesemiconductor chips, as a matter of course. This insulator film (resistpattern) may be removed after formation of the metal film by gasdeposition or plating for newly forming another insulator film, or maybe employed as the protective insulator film for the semiconductor chipsas such. According to the aforementioned method, the connecting terminalcan be readily brought into an arbitrary shape.

[0197] Thereafter the metal wires 18 are formed over the exposedportions of the electrodes 3 and the trench 11 by gas deposition (FIG.54). First ends 18 b of the metal wires 18 formed by gas deposition areconnected to the electrodes 3 in a shape responsive to the shape of theelectrodes 3. Second ends 18 a of the metal wires 18 connected toexternal devices are in contact with the support plate 5 through flatcontact potions, to define connecting terminals 18 a having a shapepreferable for connection. It is to be noted that the metal wires 18 areso formed that the connecting terminals 18 a are different in shape fromthe remaining parts of the metal wires 18 also in the case of gasdeposition, similarly to the case of wire bonding.

[0198] Thereafter the resist patterns 17 are removed, as shown in FIG.55. Then, the semiconductor chips 1 a are sealed with insulating resin 4(FIG. 56). Thereafter the support plate 5 is removed for exposing theconnecting terminals 18 a of the metal wires 18, thereby obtaining thesemiconductor devices shown in FIG. 49. While FIG. 49 shows the twosemiconductor chips 1 a holding the trench 11 therebetween, the numberof such semiconductor chips 1 a is not restricted to two but a largenumber of semiconductor chips 1 a are separated from each other andformed in the stage after removing the aforementioned support plate 5,as a matter of course.

[0199] A structure of a semiconductor device fabricated by wire bondingcan be fabricated by gas deposition. For example, FIG. 57 shows thestructure of a semiconductor device having a thermal conductor arrangedon the back surface of a semiconductor chip 1 a for the purpose of heatradiation. Both of a metal wire 18 and a connecting terminal 18a areformed by gas deposition. FIG. 58 shows the structure of a semiconductordevice having a metal wire 18, formed by gas deposition, including aconnecting terminal 18a having a side surface exposed from sealing resin4. Thus, the semiconductor device provided with the metal wire 18including the connecting terminal 18 a having the exposed side surfacecan also be formed by gas deposition.

[0200] As shown in each of the first to tenth embodiments, only asection of the wire forming the metal wire can be obtained when themetal wire is formed by wire bonding. Also as to the connectingterminal, only the bulk shape of the size obtainable by heating anddeforming the wire in the wire bonding step can be obtained. When gasdeposition is employed in place of the wire bonding as in thisembodiment, however, the size of the connecting terminal 18 a and thesectional area of the electric circuit of the metal wire 18 can bereadily changed in response to the bonding strength and the currentdensity.

[0201] When employing either gas deposition or plating, the connectingterminal may not be worked dissimilarly to the case of employing a wire.Both of the connecting terminal and the terminal part provided on theelectrode can be formed into arbitrary shapes. When gas deposition orplating is employed, however, the metal wire, which cannot be extendedin the air dissimilarly to a wire, is formed on a support layer coveringat least the main surface of the semiconductor chip. A durable insulatorfilm may be employed as this support layer, for defining a protectivelayer for the semiconductor chip as such. Alternatively, a resist filmmay be arranged as the support layer for forming the metal wire by theaforementioned gas deposition or plating and thereafter removed, forthereafter newly forming a durable insulator.

[0202] When the metal wire is formed by plating, electroplating isemployed in general and hence a metal film for defining a cathode isformed on the aforementioned support layer.

[0203] Twelfth Embodiment

[0204] Referring to FIG. 59, two semiconductor devices according to atwelfth embodiment of the present invention are opposed to each otherimmediately after removing a support plate 5. The feature of thisembodiment resides in that connecting terminals 18 c of metal wires 18formed by gas deposition are exposed from sealing resin 4 not only onbottom portions but also on upper portions.

[0205] The aforementioned semiconductor devices are fabricatedidentically to those of the eleventh embodiment up to a step similar tothat shown in FIG. 53. In other words, the steps of fabricating thesemiconductor devices according to the twelfth embodiment are identicalto those of the eleventh embodiment up to a step of exposing prescribedportions of electrodes 3 and a trench 11 and forming resist patterns 17to cover the upper and side surfaces of semiconductor chips 1 a and thecenter of the trench 11 (see FIG. 53). Thereafter the metal wires 18 areformed by gas deposition. The connecting terminals 18 c of the metalwires 18 are mounded to project upward (FIG. 60). The method of formingthe metal wires 18 including the connecting terminals 18 c is describedlater with reference to a thirteenth embodiment of the presentinvention.

[0206] Thereafter the resist patterns 17 are removed (FIG. 61), and thesemiconductor chips 1 a are sealed with the sealing resin 4 (FIG. 62).At this time, the upwardly projecting portions of the connectingterminals 18 c are rendered to project from the sealing resin 4.Thereafter the support plate 5 is removed, thereby obtaining thefragmented semiconductor devices as shown in FIG. 59.

[0207] A forwardly layered semiconductor device can be obtained byforwardly stacking the semiconductor devices shown in FIG. 59, providedwith terminals on the same upper and lower positions, as such.Alternatively, the upwardly projecting connecting terminals 18 c can beprovided on the positions of the electrodes 3.

[0208]FIG. 63 illustrates semiconductor devices having upwardlyprojecting connecting terminals 18 d provided on the positions ofelectrodes 3. The semiconductor devices shown in FIG. 63 are providedwith terminals on different upper and lower positions. A semiconductordevice having a two-layer structure can be formed by combining suchsemiconductor devices provided with terminals on different upper andlower positions shown in FIG. 63 while butting the upper surfaces of thesemiconductor devices against each other as shown in FIG. 35. Thesemiconductor device having such a two-layer structure is provided withterminals on different upper and lower positions when observed as asingle semiconductor device. Therefore, a forwardly layeredsemiconductor device can be obtained by forwardly stacking an intendednumber of such semiconductor devices as such. In other words, an evennumber of the semiconductor devices shown in FIG. 63 are stacked.

[0209] When upwardly projecting connecting terminals are formed by gasdeposition as described above, fabrication steps can be more simplifiedas compared with the case of forming two bulk terminals by wire bonding.

[0210] Thirteenth Embodiment

[0211] Referring to FIG. 64 showing a gas deposition apparatus employedfor fabricating semiconductor devices according to the thirteenthembodiment of the present invention, a deposition source 56 consistingof raw material stored in a crucible 61 and heated and melted by aheater is arranged in a deposition source chamber 66. The depositionsource chamber 66 is filled with helium, so that the raw material isvaporized into extremely fine particles, which in turn are guided to anevacuated sample chamber 64 through a transport tube 63. The fineparticles are spouted from a nozzle 67 mounted on an end of thetransport tube 63 closer to the sample chamber 64 and sprayed on asample 55 arranged on an x-y-θ stage 65.

[0212]FIG. 65 shows a step of spouting the deposition source 56 from thenozzle 67 against the sample 55 for forming a metal wire 18. In order toform the metal wire 18 by gas deposition, the nozzle 67 and the sample55 as well as the stage 65 may be relatively moved along parallelplanes.

[0213] In order to form an upwardly projecting connecting terminal 18 c,the deposition source 56 is spouted while stopping the nozzle 67 and thestage 65 as shown in FIG. 66. Consequently, the upwardly projectingconnecting terminal 18c can be readily formed.

[0214] Fourteenth Embodiment

[0215]FIG. 67 shows two semiconductor devices according to a fourteenthembodiment of the present invention holding a trench 11 therebetweenimmediately after removal of a support plate 5. The feature of thisembodiment resides in that insulator films 27 exposing electrodes 3 ofsemiconductor chips 1 a while covering the remaining parts are left inthe semiconductor devices when forming metal wires 18 by gas deposition.In each of the eleventh to thirteenth embodiments, the resist patterns17 functioning similarly to the insulator films 27 are entirely removed,followed by sealing with the sealing resin 4.

[0216] The aforementioned semiconductor devices are fabricated similarlyto those according to the eleventh embodiment up to a step similar tothat shown in FIG. 52. In other words, the semiconductor devicesaccording to the fourteenth embodiment are fabricated similarly to thoseaccording to the eleventh embodiment up to a stage of providing thetrench 11 reaching the support plate 5 in a wafer by dicing to theseparate semiconductor chips la from each other (see FIG. 52).Thereafter the semiconductor chips 1 a are covered with insulatingpatterns 27 of polyimide, for example, while exposing the electrodes 3and the center of the trench 11 along the width, as shown in FIG. 68.Then, the metal wires 18 are formed by gas deposition, to connect theelectrodes 3 with portions of the support plate 5 located on the bottomof the trench 11. Thereafter the semiconductor chips la are sealed withsealing resin 4 while leaving the insulating patterns 27 intact. Thefragmented semiconductor devices can be obtained by removing the supportplate 5, as shown in FIG. 67.

[0217] According to this embodiment, the metal wires 18 are formed bygas deposition as shown in FIG. 69 after forming the patterns of theinsulator films 27 such as polyimide films or silicon oxide films havingexcellent physical stability and chemical stability in place of thephotoresist patterns 17. Thereafter the semiconductor chips 1 a aresealed with the sealing resin 4, as shown in FIG. 70. According to thismethod, no step of removing resist patterns is required as compared withthe method employing the photoresist patterns 17. Portions around thewires 18 are not hollowed before the semiconductor chips 1 a are sealedwith the resin 4, and hence the metal wires 18 are supported bypolyimide or the like forming the insulating patterns 27. Therefore, thesemiconductor devices can be stably produced with a high yield. Further,fine and precise connection is enabled due to the formation of theaforementioned insulating patterns 27.

[0218] Fifteenth Embodiment

[0219]FIG. 71 illustrates two semiconductor devices according to afifteenth embodiment of the present invention holding a trench 11therebetween immediately after removal of a support plate 5. The featureof this embodiment resides in that sealing resin films 28 exposingelectrodes 3 of semiconductor chips 1 a while covering the remainingparts are left in the semiconductor devices when forming metal wires 18by gas deposition.

[0220] The aforementioned semiconductor devices are fabricated similarlyto those according to the eleventh embodiment up to a step similar tothat shown in FIG. 52. In other words, the semiconductor devicesaccording to the fifteenth embodiment are fabricated similarly to thoseaccording to the eleventh embodiment up to a stage of providing thetrench 11 reaching the support plate 5 in a wafer by dicing to separatethe semiconductor chips 1 a from each other (see FIG. 52). Thereafterthe semiconductor chips 1 a are covered with sealing resin patterns 28by screen printing, for example, while exposing the electrodes 3 and thecenter of the trench 11 along the width, as shown in FIG. 72. Then, themetal wires 18 are formed by gas deposition, to connect the electrodes 3with portions of the support plate 5 located on the bottom of the trench11 (FIG. 73). Thereafter the fragmented semiconductor devices can beobtained by removing the support plate 5 while allowedly leaving thesealing resin patterns 28 intact, as shown in FIG. 71.

[0221] According to this embodiment, the sealing resin patterns 28 areemployed in place of the photoresist patterns 17 or the insulator filmpatterns 27 of polyimide or the like. When the sealing resin patterns 28are employed, the semiconductor devices can be fabricated through stepsshorter than those employing the remaining patterns 17 or 27. Atpresent, however, the sealing resin patterns 28 can be formed by onlyscreen printing relatively inferior in dimensional accuracy. Therefore,the method according to the fifteenth embodiment cannot deal withrefinement of the electrodes 3 at present. Further, only the metal wires18 formed by gas deposition are located on the electrodes 3, and hencethe semiconductor devices according to the fifteenth embodiment areinferior in reliability and durability to those according to theremaining embodiments.

[0222] Sixteenth Embodiment

[0223] Referring to FIG. 74 showing a sixteenth embodiment of thepresent invention, the upper surfaces of semiconductor devices identicalto those shown in FIG. 71 are opposed to each other for forming amultilayer structure by connecting exposed metal wires with each otherby solder 37. When a semiconductor device of this two-layer structure isobserved as a single semiconductor device, connecting terminals areprovided on the same upper and lower positions. Therefore, a multilayersemiconductor device having even layers can be readily obtained bysuccessively stacking such semiconductor devices as such. Thesemiconductor device can also be improved in reliability and durabilitydue to the solder 37 covering the metal wires.

[0224] Seventeenth Embodiment

[0225]FIG. 75 illustrates two semiconductor devices according to aseventeenth embodiment of the present invention holding a trench 11therebetween immediately after removal of a support plate. The featureof this embodiment resides in that metal wires are formed byelectroplating.

[0226] The aforementioned semiconductor devices are fabricatedidentically to those according to the fifteenth embodiment up to a stepsimilar to that shown in FIG. 72. In other words, the semiconductordevices according to the seventeenth embodiment are fabricated similarlyto those according to the fifteenth embodiment up to a stage of forminginsulator film patterns 28 of polyimide, for example, while exposingelectrodes 3 and the center of the trench 11 along the width (see FIG.72). Then, a metal film 31 or the like defining cathodes forelectroplating is formed by vapor deposition (FIG. 76). Then, resistpatterns 17 are formed on portions other than those for forming themetal wires by electroplating and connecting the same (FIG. 77).

[0227] Thereafter portions of the metal film 31 not covered with theresist patterns 17 are employed as cathodes for forming connectionpatterns of the metal wires by electroplating (FIG. 78). Then, theresist patterns 17 are removed (FIG. 79). Further, connection patternsof metal films 38 formed by electroplating are employed as masks forremoving the metal film 31 employed as the cathodes for electroplatingby etching (FIG. 80). The fragmented semiconductor devices can beobtained by sealing semiconductor chips 1 a with sealing resin 4 (FIG.81) and removing the support plate 5, as shown in FIG. 75.

[0228] When the metal wires are formed by electroplating as describedabove, the number of fabrication steps is increased. However, finerworking can be performed as compared with wire bonding or gas depositiondue to employment of photolithography.

[0229] Eighteenth Embodiment

[0230]FIG. 82 illustrates two semiconductor devices according to aneighteenth embodiment of the present invention holding a trenchtherebetween immediately after removal of a support plate 5. The featureof this embodiment resides in that metal wires are formed byelectroplating.

[0231] The aforementioned semiconductor devices are fabricatedidentically to those according to the seventeenth embodiment up to astep similar to that shown in FIG. 79. In other words, the semiconductordevices according to the eighteenth embodiment are fabricated similarlyto those according to the seventeenth embodiment up to a stage offorming connection patterns of metal wires by electroplating whileemploying portions of a metal film 31 not covered with resist patterns17 as cathodes and thereafter removing the resist patterns 17.Thereafter a second resist pattern 57 having openings above electrodes 3of semiconductor chips 1 a is formed as shown in FIG. 83. Then,on-electrode terminals 41 are formed in the openings by secondelectroplating (FIG. 84).

[0232] Thereafter the second resist pattern 57 is removed, as shown inFIG. 85. Then, the semiconductor chips 1 a are sealed with sealing resin4 while exposing the on-electrode terminals 41 (FIG. 86). The fragmentedsemiconductor devices can be obtained by thereafter removing the supportplate 5, as shown in FIG. 82. The fragmented semiconductor devices shownin FIG. 82 are provided with terminals on different upper and lowerpositions.

[0233]FIG. 87 shows a modification of the semiconductor devices shown inFIG. 82. Referring to FIG. 87, upper connecting terminals 58 are formedon connecting terminals 38 a formed on portions of a support platelocated on the bottom of a trench. The semiconductor devices shown inFIG. 87 can be formed by providing a second resist pattern 57 to haveopenings above the connecting terminals 38 a.

[0234] The semiconductor devices shown in each of FIGS. 82 and 87 can bebasically formed by performing photolithography twice and electroplatingtwice. When forming multilayer connecting terminals by electroplating,not only superior fine working can be performed as compared with wirebonding or gas deposition but also the size of connecting terminalsexposed on the upper surfaces can be readily controlled. Wire bonding islimited by the wire diameter, while the diameter of deposition materialemployed for forming connecting terminals by gas deposition is graduallyreduced upward. In the gas deposition, therefore, the portions of theconnecting terminals exposed on the upper surface of the sealing resin 4are limited in size. According to electroplating, the connectingterminals 38 a can be formed with no fluctuation in size by increasingthe resolution of the resist pattern 57, regardless of the height of theon-electrode terminals 41.

[0235] Nineteenth Embodiment

[0236] FIGS. 88 to 93 illustrate a semiconductor device according to anineteenth embodiment of the present invention and first to fifthmodifications thereof respectively. According to this embodiment, astructure formable by wire bonding or gas deposition is formed byelectroplating.

[0237] In the semiconductor device according to the nineteenthembodiment shown in FIG. 88, a metal wire is formed by electroplating byarranging a photoresist pattern in place of an insulator film pattern 17consisting of polyimide, for example. The photoresist pattern is removedafter etching and removing a part of a metal film 31 employed as acathode through a mask of a metal wire 38 formed by electroplatingbefore sealing a semiconductor chip 1 a with sealing resin 4. Thesemiconductor chip 1 a is sealed with the sealing resin 4 after removalof the photoresist pattern.

[0238] When arranging the same sealing resin 4 on the surface and theback surface of the metal wire 38 as described above, a possibility ofdisconnecting the metal wire 38 by stress resulting from thermal straincan be reduced.

[0239] In the semiconductor device according to the first modificationof the nineteenth embodiment shown in FIG. 89, a connecting terminal 38a is partially exposed on the side surface of the semiconductor device.According to this structure, bonding strength can be improved similarlyto the case of wire bonding or gas deposition.

[0240] The feature of the semiconductor device including a metal wireformed by electroplating according to the second modification of thenineteenth embodiment shown in FIG. 90 resides in that a step isprovided between a semiconductor chip 1 a and an insulator film pattern27 of polyimide or the like on the back surface of the semiconductordevice. The connecting terminal 38 a projects due to the presence ofsuch a step, thereby simplifying connection. Such simplification ofconnection attained by the projecting structure of the connectingterminal 38 a is not restrictive but can be obtained in any method offorming the metal wire.

[0241] In the semiconductor device including a metal wire formed byelectroplating according to the third modification of the nineteenthembodiment shown in FIG. 91, a plate 6 having excellent thermalconductivity is arranged on the back surface of a semiconductor chip 1 afor the purpose of heat radiation. The heat radiation property of thesemiconductor chip 1 a can be improved due to the arrangement of theplate 6. Such improvement of the heat radiation property due to thearrangement of the aforementioned plate 6 is not restrictive either butcan be obtained in any method of forming the metal wire.

[0242] The feature the semiconductor device including a metal wire 38formed by electroplating according to the fourth modification of thenineteenth embodiment shown in FIG. 92 resides in that the upper, sideand lower surfaces of an upper connecting terminal 58 provided on aconnecting terminal 38 a are exposed from sealing resin 4. When theupper connecting terminal 58 is exposed in the aforementioned manner,connection is enabled on a number of portions of the upper connectingterminal 58 so that the semiconductor device can be loaded on anycircuit board. This function is not restrictive either but can beobtained in any method of forming the metal wire.

[0243] In the semiconductor device according to the fifth modificationof the nineteenth embodiment shown in FIG. 93, an opening of a secondresist pattern can be displaced outward beyond a first electroplatingpattern in fabrication of a semiconductor device similar to that shownin FIG. 87. In the semiconductor device shown in FIG. 93, the sidesurface of an upper connecting terminal 58 is not entirely exposed,dissimilarly to the semiconductor device shown in FIG. 92. An upperportion of the side surface of the upper connecting terminal 58 iscovered with sealing resin 4.

[0244] According to the semiconductor device shown in FIG. 93, a bondingagent such as solder can be prevented from creeping up toward the uppersurface of the upper connecting terminal 58 while obtaining high bondingstrength and excellent bondability on exposed portions of the side andlower surfaces of the upper connecting terminal 58.

[0245] Twentieth Embodiment

[0246] Referring to FIG. 94, the feature of a twentieth embodiment ofthe present invention resides in that positions of metal wires 2, 18 and38 connecting electrodes of semiconductor chips and a support plate aredisplaced between adjacent semiconductor chips for alternatelyconnecting the bottoms of trenches to the support plate. The trenchescan be reduced in width due to the aforementioned arrangement of themetal wires 2, 18 and 38.

[0247] A method of fabricating semiconductor devices according to thisembodiment can allowedly be carried out by any of wire bonding, gasdeposition and plating. Particularly plating employing photolithographyis so excellent in fine workability that the semiconductor devices canbe fabricated without widening electrode pitches of semiconductor chipsas compared with wire bonding and gas deposition. Wire bonding and gasdeposition are relatively inferior in fine workability as compared withplating, and hence electrode pitches must be widened when trenches arereduced in width, relatively disadvantageously for semiconductor chipshaving numbers of electrodes.

[0248] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip including a semiconductor circuit having a prescribedfunction and an electrode on a main surface; a metal wire having a firstend connected with said electrode and a second end having a connectingterminal connected with an external device; and an insulator covering atleast said main surface of said semiconductor chip, wherein saidconnecting terminal provided on said second end of said metal wire is apart formed while keeping a state integrated with the remaining part ofsaid metal wire, and exposed on a bottom surface opposite to the uppersurface of said insulator.
 2. The semiconductor device according toclaim 1, wherein said metal wire is a wire formed by wire bonding, andsaid connecting terminal is a bulk connecting terminal formed by workingand bulking a part of said wire in continuation with said wire.
 3. Thesemiconductor device according to claim 1, wherein said metal wire andsaid connecting terminal are formed by either gas deposition or plating.4. The semiconductor device according to claim 1, wherein an exposedsurface of said connecting terminal is located on a position projectingoutward beyond the back main surface of said semiconductor chip oppositeto said main surface.
 5. The semiconductor device according to claim 1,wherein a plate member is arranged in contact with the back main surfaceof said semiconductor chip opposite to said main surface, and exposedfrom said bottom surface.
 6. The semiconductor device according to claim1, wherein an exposed part of said connecting terminal is clad withsolder.
 7. The semiconductor device according to claim 1, furthercomprising an upper connecting terminal in contact with the upperportion of said connecting terminal.
 8. A semiconductor device formed bystacking at least two semiconductor devices according to claim 7employed as unit semiconductor devices, so that said connecting terminalof first said unit semiconductor device is connected to said upperconnecting terminal of second said unit semiconductor device.
 9. Thesemiconductor device according to claim 1, further comprising anon-electrode terminal on said electrode.
 10. A semiconductor device,employing a unit semiconductor device formed by the semiconductor deviceaccording to claim 9, comprising a face-symmetrical semiconductor devicehaving face-symmetrical arrangement with respect to said unitsemiconductor device in relation to a plane parallel to said mainsurface and said unit semiconductor device, having either an uppersurface butt joint structure formed by connecting and stacking anon-electrode terminal of said face-symmetrical semiconductor device toand on said on-electrode terminal of said unit semiconductor device or abottom surface butt joint structure formed by connecting and stacking aconnecting terminal of said face-symmetrical semiconductor device to andon said connecting terminal of said unit semiconductor device.
 11. Thesemiconductor device according to claim 1, wherein an outer end of saidconnecting terminal is further exposed from the side surface of saidinsulator.
 12. A semiconductor device comprising at least twosemiconductor devices according to claim 11 and a wall circuit boardincluding a circuit wire therein and standing to intersect with thesurfaces of said semiconductor chips so that exposed side surfaces ofsaid connecting terminals of said semiconductor devices are connected tosaid wall circuit board and said semiconductor devices are mounted in alayered manner.
 13. A method of fabricating semiconductor devices forfabricating at least two semiconductor devices from a semiconductorsubstrate including at least two semiconductor circuit areas providedwith electrodes having prescribed functions for attaining electricalconnection with an external device arranged on a first main surface,comprising steps of. bonding a support plate to a second main surface ofsaid semiconductor substrate opposite to said first main surface;forming a trench for separating said at least two semiconductor circuitareas into individual said semiconductor circuit areas to expose saidsupport plate around said semiconductor circuit areas; connecting saidelectrodes and said support plate exposed in said trench with each otherby a metal wire; and removing said support plate.
 14. The method offabricating semiconductor devices according to claim 13, connecting abulk wire formed by partially melting and bulking a wire around a partto be connected to said support plate by wire bonding in said step ofconnecting said electrodes and said support plate with each other bysaid metal wire.
 15. The method of fabricating semiconductor devicesaccording to claim 13, further comprising a step of covering said firstmain surface of said semiconductor substrate with an insulator filmbefore said step of connecting said electrodes and said support platewith each other by said metal wire, and forming a metal film coming intocontact with upper portions of said insulator film, said electrodes andsaid support plate by either gas deposition or plating in said step ofconnecting said electrodes and said support plate with each other bysaid metal wire.
 16. The method of fabricating semiconductor devicesaccording to claim 13, bonding said support plate by anode coupling insaid step of bonding said support plate to said second main surface ofsaid semiconductor substrate opposite to said first main surface. 17.The method of fabricating semiconductor devices according to claim 13,forming said trench with a dicing saw in said step of forming saidtrench.
 18. The method of fabricating semiconductor devices according toclaim 13, further comprising a step of sealing said metal wire and saidsemiconductor circuit areas with an insulator, for applying flowablepolymer resin to prescribed areas by screen printing and covering saidprescribed areas with said polymer resin in said sealing step.
 19. Themethod of fabricating semiconductor devices according to claim 13,further comprising a step of sealing said metal wire and saidsemiconductor circuit areas with an insulator, for covering the overallsurface of said semiconductor substrate with said insulator in said stepof sealing said metal wire and said semiconductor circuit areas withsaid insulator and removing a prescribed part of said insulator with adicing saw in any subsequent step for separating said at least twosemiconductor circuit areas into individual said semiconductor circuitareas.
 20. A method of fabricating semiconductor devices for fabricatingat least two semiconductor devices from a semiconductor substrateincluding at least two semiconductor circuit areas provided withelectrodes having prescribed functions for attaining electricalconnection with an external device arranged on a first main surface,comprising steps of: separating said semiconductor substrate intoindividual said semiconductor circuit areas by cutting; bonding asupport plate to a second main surface of said semiconductor substrateopposite to said first main surface; connecting said electrodes and saidsupport plate exposed in a-trench with each other by a metal wire; andremoving said support plate.